It is often desirable to provide software code or other data that is loaded from external memories and executed or otherwise accessed by processing circuitry embedded within integrated circuits. For certain environments including such embedded processors, hardware data integrity mechanisms are desirable for the data stored within the external, off-chip memories. Traditional error correcting codes (ECC) can be used for implementations needing such hardware enforced data integrity measures. However, many non-volatile and/or random access (RAM) memory devices that are used for external memories have low pin count interfaces, for example, 1-bit, 2-bit, 4-bit, or 8-bit data buses, based on package pin constraints, resulting in difficulties in implementing traditional ECC mechanisms that rely upon relatively wide data paths to efficiently analyze and correct bit errors within the external memories.